1. Technical Field
The present invention relates to methods and apparatuses for timing analysis of electronic circuits. In particular, the present invention relates to a system for performing timing analysis using a simulated waveform.
2. Background Information
Timing analysis in general is used in the context of analysis of electronic circuits, for example during the design of electronic circuits. In such electronic circuits, the timing of the circuit has to be checked such that signals generated by one circuit element reach another circuit element at an appropriate time. A simple example for this situation is shown in FIG. 1, where a circuit element 24 generates a signal d to be sampled in a flipflop 23 depending on a clock signal clk. In other words, at a time defined by the clock signal clk, flipflop 23 samples signal d and outputs the sampled value q. To ensure a correct sampling of the signal d, the signal d has to be present in a steady state (i.e. without state transitions) a certain time before and after the sampling time defined by the clock signal clk. The time during which signal d is present before the sampling time is commonly referred to as setup time, whereas the time during which the signal d is present after the sampling time is referred to as hold time.
When designing electronic circuits, it is desired to evaluate the functioning of the circuit as soon as possible before the actual physical implementation of the circuit. A general method for evaluating circuits is so-called analog simulation, where a transistor level netlist of a circuit is processed. The components of the circuit like transistors are represented as differential equations, wherein a single transistor may be characterized by a plurality of parameters. Analog simulation then solves these differential equations for example by employing a time step method.
However, for modern electronic integrated circuits like microprocessors which may comprise millions of transistors being interconnected a full analog simulation for all possible inputs of the circuit with current computing equipment would take too much time to be practical. Therefore, to perform a timing analysis of complex circuits, for example synchronous digital circuits, so-called static timing analysis (STA) is conventionally employed. In static timing analysis, the basic principle is to only consider so-called “extremal” timing events and not to analyze all possible input patterns at input terminals of a circuit design concurrently. In particular, no series of switchings at an input is analyzed, but only a single switching of one (or possibly more) input(s), while the remaining input(s) are held constant. Extremal timing events in this respect are those input patterns which lead to the earliest or latest arrival of a signal at a given receiver cell like flipflop 23 of FIG. 1. If these earliest and latest arrivals fulfill the timing requirements of the circuit regarding arrival time, all other timing events or configurations are assumed to also fulfill the requirements. The computational effort of static timing analysis is linear with respect to the complexity of the design and not exponential as it would be for a full analog simulation.
In conventional static timing analysis, a circuit design is broken down into so-called stages, a stage being defined as a circuit portion having an input which may be an input of a so-called driving cell generating a signal and at least one output, the outputs being either outputs of the circuit or connected to inputs of further circuit elements designated receiver cells. For example, FIG. 1 may be seen as representing such a stage, where circuit element 24 is the driver cell and flipflop 23 is the receiver cell. The circuit design is then processed stage by stage according to a so-called topological sorting of the stages starting at the input terminals of the electronic circuits such that the input signal for a subsequent stage is available for the processing of said subsequent stage.
In static timing analysis first of all the propagation of the signals through the stages, for example through gates and networks in the stages, is calculated independently of a clock signal, this step being designated delay calculation. Then, these results are evaluated in the context of the clock signals and further design constraints used, for example to evaluate whether a signal fulfils the setup time and hold time requirements for a given clock signal.
In conventional static timing analysis signal transitions from one state to another state (i.e. from a logical 0 to a logic 1 in the case of a digital signal) are approximated as ramps, and in the case of voltage signals a single voltage point is conventionally taken as a delay threshold for delay measurement of the transition. This situation is depicted in FIG. 2, where a signal 21 changes from 0 representing a logic 0 to a positive voltage VDD representing a logic 1. In the exemplary diagram of FIG. 2, the ramp of signal 21 is chosen such that it crosses the actual signal which corresponds to curve 22 at voltage VI, Vh. VI may be set to 10% of VDD, and Vh may be set to 90% of VDD. The time between signal 21 reaching VI and signal 21 reaching Vh is taken as a transition time, in the present case indicating the time necessary to change from a logic 0 to a logic 1. The delay threshold in the example shown is set to the point where signal 21 crosses VT=VDD/2, the corresponding delay time being designated t1 in FIG. 2. However, other values for VT may also be chosen. Therefore, in static timing analysis it would for example be evaluated whether t1 is within a desired time frame to meet, for example, a required setup time. Through the approximation of signals as ramps, the signals may be characterized by a single parameter like the above-mentioned transition time or slew or by only a few parameters.
Additionally, static timing analysis uses a library where the electrical or timing characteristics of a plurality of possible cells like flipflops, combinational gates or other circuit elements which may comprise a plurality of transistors are stored. When processing a stage, the characteristics of the cells of this stage are taken from the library.
As circuits become more and more complex and clock rates increase, timing in circuits often becomes more critical. Therefore, there exists a general need for methods and apparatuses for timing analysis of electronic circuits which allow a precise analysis even of complex circuits.